Jul. 27 at 2:54 PM
AI is moving deeper into semiconductor design.
$SNPS just unveiled two autonomous chip-design workflows with
$MSFT, with
$AMD evaluating the technology for next-generation products.
The first workflow automates debug closure and reportedly reduced cycle times by 25%-40% in early testing.
The second uses Fusion Compiler on Azure to automate implementation, timing closure, and design optimization.
These are the first EDA applications available for evaluation on Microsoft Discovery.
Separately,
$SNPS expanded its partnership with
$INTC, adding certified EDA flows for Intel 14A, EMIB, EMIB-T packaging, and new IP support including 224G SerDes, PCIe 7.0, USB 4, and eUSB.
The bigger picture: AI is not only creating demand for chips — it's changing how chips are designed.
EDA, advanced packaging, and semiconductor automation could become critical bottlenecks in the next AI cycle.
Watching
$SNPS,
$MSFT,
$AMD,
$INTC closely.
Do you think EDA will become the next major AI infrastructure winner?
